1. Field of the Invention
The present invention relates in general to saving power of a semiconductor memory device, and more particularly to a buffer control circuit and method for a synchronous dynamic random access memory (referred to hereinafter as DRAM) with a power saving function, in which a signal generator generates a command/address input buffer control signal in an improved manner to reduce the amount of current being consumed at a standby state of the synchronous DRAM. The present invention is applicable to all synchronous memory devices.
2. Description of the Prior Art
Generally, a synchronous DRAM basically has a power down mode for saving power of the device. The power down mode has the effect of saving a considerable amount of power as a whole by reducing the amount of current being consumed at a standby state of the synchronous DRAM.
The power down mode is performed according to a logic state of a clock enable signal which is a "high" active signal. When the clock enable signal is high in logic, a main clock signal is transferred from the outside of a chip to the inside thereof, and the input of a command and address is enabled.
To the contrary, in the case where the clock enable signal is low in logic, the main clock signal is not transferred from the outside of the chip to the inside thereof. Also, command/address input buffers enter an inactive state (off state) to reduce a static current consumption amount. In other words, the power down mode is performed when the clock enable signal is low in logic.
However, when the present mode is not the power down mode, namely, when the clock enable signal is high in logic, the command/address input buffers are made active, resulting in continuous power consumption.
The reason for this is that the command/address input buffers must always be made active at the standby state to be ready to input a new command and a new address.
Further, a command input clock point has to be synchronized with a chip select signal.
As a result, under the above-mentioned prescription, namely, unless the specification is modified, the existing techniques have no choice but to depend on the logic state of the clock enable signal to generate a buffer control signal. In other words, the buffer control signal is conventionally generated by using a second or third signal derived from the clock enable signal.
In brief, when the clock enable signal is high in logic, the current mode is not the power down mode and all the buffers are at the input standby state. For this reason, a standby current flows continuously at the buffer stage, thereby increasing the power consumption amount.
Particularly, such a phenomenon results in a considerable amount of power consumption in a system employing a battery as a power source.
The cause of current being consumed at the standby state of the input buffers as stated previously is as follows.
Most devices manufactured at the present are composed of CMOS transistor logics. The internal logics of the devices have a rail-to-rail operating characteristic where the amount of static current consumed in all intervals except logic transition intervals is nearly zero.
However, an input buffer for receiving a signal from the outside of the device has a different logic state from that of the internal logic, as follows.
First, the input buffer has a value higher than or equal to "VIH" at a high logic state. Here, "VIH" signifies a minimum voltage value for indicating that the input buffer is high in logic. Accordingly, the input buffer consumes a static current at the high logic state where it has a voltage value between "VIH" and "VDD".
Similarly, the same phenomenon appears at a low logic state.
As a result, a switch capable of selectively operating the buffer has been proposed by most buffer design techniques to reduce the static current amount.